This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. xc2xa7 119 from applications entitled Interprocessor Communication System earlier filed in the Korean Industrial Property Office on the 29th day of December 1997, and there duly assigned Serial Nos. 76049-1997 and 76050-1997, and on the 18th day of July 1998, and there duly assigned Serial No. 29037-1998.
1. Technical Field
The present invention relates to an interprocessor communication device in a digital system having at least two processors, and more particularly to an interprocessor communication device with a message passing network allowing rapid transfer of messages between a plurality of processors.
2. Related Art
For high performance and real-time data processing, two or more processor modules can be loaded into a digital system such as a digital data transmission system, a digital switching system, and a network server for processing data from a plurality of clients. Each processor module includes at least one microprocessor.
In order to rapidly process a large amount of digital data, the digital system should be provided with an interprocessor communication (IPC) device for transferring messages between a plurality of processor modules processing elements after their own functions. As is known, interprocessor communication is generally implemented through a shared memory like a dual port random access memory (RAM), but this allows no concurrent access of two processors to data, thus lowering interprocessor communication efficiency.
Exemplars of recent efforts in the art include U.S. Pat. No. 5,787,300 for a Method and Apparatus for Interprocess Communications in a Database Environment issued to Wijaya, U.S. Pat. No. 5,778,429 for a Parallel Processor System Including a Cache Memory Subsystem That Has Independently Addressable Local and Remote Data Areas issued to Sukegawa et al., U.S. Pat. No. 5,745,779 for a Network Subsystem for Parallel Processor System and Network System for Parallel Processor System issued to Katori, U.S. Pat. No. 5,745,778 for an Apparatus and Method for Improved Cpu Affinity in a Multiprocessor System issued to Alfieri, U.S. Pat. No. 4,507,728 for a Data Processing System for Parallel Processing of Different Instructions issued to Sakamoto et al., U.S. Pat. No. 5,742,766 for a Parallel Computing System for Synchronizing Processors by Using Partial Switch Circuits for Broadcasting Messages after Receiving Synchronization Signals and Judging Synchronization Thereof issued to Takeuchi et al., U.S. Pat. No. 5,630,156 for a Process for Parallel Operation of Several Computation Units, Especially in Image Processing, and Corresponding Architecture issued to Privat et al., U.S. Pat. No. 5,287,532 for a Processor Elements Having Multi-byte Structure Shift Register for Shifting Data Either Byte Wise or Bit Wise with Single-bit Output Formed at Bit Positions Thereof Spaced by One Byte issued to Hunt, and U.S. Pat. No. 5,249,301 for a Processing Communication System Having a Plurality of Memories and Processors Couples Through at Least One Feedback Shift Register Provided from Ring Configured Input Stations issued to Keryvel et al.
While these recent efforts provide advantages, I note that they fail to adequately provide an enhanced, efficient interprocessor communication device with a message passing network allowing rapid transfer of messages between a plurality of processors.
Therefore, an object of the present invention is to provide an interprocessor communication (IPC) device enabling rapid transfer of a data message between processors in a digital system having at least two processors.
Another object ofthe present invention is to provide an interprocessor communication device having a rotation bus interface module (RBIM) which switches two adjacent processors to memory system buses to mutually transmit a message at high speed.
Still another object of the present invention is to provide an interprocessor communication device in which messages can be rapidly transmitted between a plurality of processors over a message passing network.
To achieve the above objects, there is provided an interprocessor communication device. In the interprocessor communication device, a plurality of processors are connected to processor buses for an address signal, a data signal, and a control signal, and receives/outputs handshake signals for transmitting/receiving a message to/from an adjacent processor. A plurality of memory blocks are connected to memory buses for an address signal, a data signal, and a control signal and stores/outputs data upon input of an address signal and a control signal. A rotation bus interface module, connected between the processor buses and the memory buses, switches the memory buses connected to the processor buses in response to handshake signals received from two adjacent processors to allow the processors exclusively to access the memory blocks.
To achieve these and other objects in accordance with the principles of the present invention, as embodied and broadly described, the present invention provides an apparatus enabling communication between processors, comprising: a plurality of processor units receiving and transmitting address signals, data signals, and control signals; a plurality of memory units storing message data corresponding to said data signals, said storing being in accordance with said address signals and control signals; and an interface unit conveying said message data from a source processor unit selected from among said plurality of processor units to said plurality of memory units and then from said plurality of memory units to a destination processor unit selected from among said plurality of said processor units in accordance with intercommunication signals, said interface unit receiving and transmitting said intercommunication signals from and to said plurality of processor units.
To achieve these and other objects in accordance with the principles of the present invention, as embodied and broadly described, the present invention provides an apparatus enabling communication between processors, comprising: a plurality of processor units receiving and transmitting address signals, data signals, and control signals; a plurality of interface units, each interface unit among said plurality of interface units conveying message data from a source processor unit selected from among said plurality of processor units to a destination processor unit selected from among said plurality of said processor units in accordance with intercommunication signals, said interface unit receiving and transmitting said intercommunication signals from and to said plurality of processor units, said message data corresponding to said data signals, address signals, and control signals, said plurality of interface units including a first interface unit and a second interface unit; a plurality of reporting buffers, each reporting buffer among said plurality of reporting buffers being connected to one processor unit among said plurality of processor units, temporarily storing message data to be output to one interface unit selected from among said plurality of interface units; a plurality of operation buffers, each operation buffer among said plurality of operation buffers being connected to one processor unit among said plurality of processor units, temporarily storing message data received from one interface unit selected from among said plurality of interface units; and a plurality of message passing units, wherein a first message passing unit among said plurality of message passing units is connected to a first reporting buffer and a first operation buffer selected from among said plurality of reporting and operation buffers, said first message passing unit receiving first message data from said first interface unit, transmitting said first message data to one of said first reporting buffer, said first operation buffer, and said second interface unit.